A processor may include multiple registers, which may be implemented as an array of memory bit cells, referred to as a register file. A register file may be implemented with static random access memory (SRAM) bit cells having dedicated or decoupled read and write ports, which may be implemented 8 transistor devices, also referred to as dual-port or 8T bit cells. A dual-port or 8T bit cell may provide faster read (RD) and write (WR) completion times, and may permit a lower operating voltage than a single access port or 6T bit cell.
Integrated circuits are being implemented with increasingly smaller sizes, which may tend to increase variations in die-to-die (D2D) and within-die (WID) process parameters. The variations may be at least partially mitigated with larger-size devices for read and write ports, allowing the circuits to operate at low voltage but at the potential cost of a higher power at high performance mode with higher switching capacitance.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears